Verification that builds confidence before tape-out.
Harmonie Design Labs provides structured verification services for ASIC, SoC, digital IP, and FPGA development programs.
We develop verification strategies and environments that assess whether a design behaves according to its approved specification across expected operating modes, interfaces, configurations, and corner cases.
Our team can manage the complete verification program, contribute to a defined block or subsystem, or independently review an existing verification environment before tape-out.
- Verification planning and architecture
- SystemVerilog and UVM testbench development
- Directed and constrained-random verification
- Functional, code, and assertion coverage
- Assertion-based verification
- Formal verification for selected properties
- Block, subsystem, and full-chip verification
- Protocol and interface verification
- Clock-domain and reset-domain verification
- Regression development and automation
From specification to verification closure
Effective verification begins with a clear definition of what the design must do and how completion will be measured.
A collection of passing simulations does not, by itself, demonstrate that a design has been sufficiently verified. Requirements must be mapped to test scenarios, checkers, assertions, and measurable coverage objectives.
Harmonie Design Labs builds the verification process around traceable requirements and defined completion criteria. This creates a structured path from the initial verification plan to final sign-off.
Define the Verification Strategy
We review the design specification, architecture, operating modes, interfaces, clock domains, reset behaviour, expected error conditions, and integration requirements. Verification risks are identified before extensive testbench development begins.
Build and Execute the Environment
We develop the required verification environment using SystemVerilog, UVM, assertions, reference models, scoreboards, monitors, and reusable verification components where appropriate.Tests are developed to exercise expected behaviour, error handling, configuration combinations, interface activity, boundary conditions, and difficult-to-reach scenarios.Regressions are executed continuously so that design changes can be assessed against the wider verification environment.
Analyse, Close, and Sign Off
Verification results are reviewed against the approved plan and coverage objectives.Failures are analysed to distinguish design defects, testbench issues, specification ambiguity, and environmental problems. Uncovered functionality is investigated and addressed through additional stimulus, assertions, formal analysis, or verification-plan updates.The verification program is considered complete only when the agreed sign-off criteria have been reviewed and documented.
Verification Methods
Different design risks require different verification techniques. We select and combine methods according to the architecture, complexity, project stage, and sign-off requirements.
Functional Verification
Functional verification assesses whether the design behaves according to the specification under expected and exceptional operating scenarios.
The environment may include:
- Directed tests
- Constrained-random stimulus
- Self-checking testbenches
- Reference models
- Scoreboards
- Protocol monitors
- Functional coverage
- Error injection and recovery scenarios
Assertion-Based Verification
Assertions express expected design behaviour as properties that can be checked during simulation or formal analysis.
They are particularly useful for:
- Interface rules
- Control sequences
- Timing relationships
- Protocol compliance
- Illegal-state detection
- Safety and consistency conditions
Formal Verification
Formal methods may be applied to selected properties where simulation alone is unlikely to explore every relevant state.
Formal verification is applied where it provides measurable technical value rather than as a default method for every block.
Typical uses include:
- Control logic
- State machines
- Arbitration behaviour
- Register consistency
- Protocol properties
- Deadlock and reachability analysis
Coverage-Driven Verification
Coverage provides measurable visibility into what has and has not been exercised.
Coverage numbers are not treated as the objective on their own. They are interpreted against the verification plan and the technical risk of the design.
We assess multiple coverage dimensions according to the project:
- Functional coverage
- Code coverage
- Assertion coverage
- State and transition coverage
- Interface and protocol coverage
- Configuration coverage
Flexible Engagement Models
Harmonie Design Labs can support verification programs through several engagement models.
Complete Verification Ownership
We define and execute the complete verification program, from planning and environment architecture through regression, coverage closure, and sign-off.
Block or Subsystem Verification
We take responsibility for a defined IP block, interface, digital subsystem, or integration level within a wider customer-led verification program.
Verification Team Extension
Our engineers work within the customer’s existing methodology, repositories, development tools, review processes, and regression infrastructure.
Verification Review and Audit
We independently assess an existing verification plan and environment before tape-out.
Formal Verification Support
We contribute formal analysis for selected blocks or properties that are difficult to verify sufficiently through simulation alone.
Why Verification Quality Matters
A design may compile, synthesize, and pass its initial tests while still containing functional defects that appear only under specific configurations or event sequences.
A structured verification process reduces these risks before the design reaches tape-out.
The objective is not to generate the largest number of tests. It is to build sufficient, measurable evidence that the design behaves as intended within the agreed scope.
Common verification risks include:
- Incomplete or ambiguous specifications
- Features that are not mapped to tests
- Insufficient error and recovery scenarios
- Unverified clock-domain interactions
- Reset sequences that are not fully exercised
- Configuration combinations omitted from regressions
- Protocol corner cases
- Coverage targets without meaningful closure analysis
- Testbench defects masking design problems
- Late changes that are not fully re-verified
Frequently asked questions
Yes. We can define and manage the verification strategy, testbench architecture, test development, regression process, coverage closure, and sign-off documentation.
Yes. We can review, extend, maintain, or complete an existing UVM environment. We can also develop new verification components within the customer’s current architecture.
No. The methodology is selected according to the design and project requirements. A project may combine directed testing, UVM, assertions, formal verification, static checks, and gate-level simulation.
Yes. We can verify an individual block, interface, subsystem, or complete digital design. The scope and integration boundaries are defined at the beginning of the engagement.
Yes. Formal techniques can be applied to selected properties, control structures, interfaces, registers, equivalence checks, and difficult-to-reach conditions where they provide clear value.
Yes. We can perform an independent verification review covering the plan, traceability, tests, assertions, coverage, regressions, known issues, and sign-off criteria.
Yes. Depending on the project scope, we can support post-synthesis or post-layout gate-level simulation, timing-aware scenarios, reset verification, and final pre-tape-out checks.
Verification primarily addresses the design before tape-out. Physical first-silicon testing and electrical characterization are covered under our Lab Validation capability. The two activities can be connected within a complete ASIC development program.
