Silicon-on-insulator is the default answer for high-temperature integrated circuits, and it is usually the right one. It is worth understanding why, because the reasons are specific — and because the drawbacks are specific too.
The two problems SOI solves
In bulk CMOS, every source and drain diffusion forms a reverse-biased junction with the substrate or the well. Those junctions leak, and their leakage rises exponentially with temperature. The total junction area facing the substrate is large, so the aggregate leakage is large.
Silicon-on-insulator puts a buried oxide layer under the active silicon. Devices sit in isolated islands, and the junction area facing the substrate disappears. What remains are the much smaller sidewall junctions. The reduction in junction leakage is typically expressed in orders of magnitude rather than percentages, and it is the single biggest reason SOI dominates high-temperature analog.
The second problem is latch-up. Bulk CMOS contains a parasitic four-layer thyristor formed by the p and n regions of the well structure. Its trigger and holding currents fall as temperature rises, because the parasitic bipolar gains increase and the well and substrate resistances increase. In SOI the buried oxide breaks the structure. The parasitic thyristor does not exist, so latch-up is not a failure mode that has to be designed against.
There is a third, quieter benefit: junction capacitance to the substrate is much lower, which helps speed and reduces dynamic power. At high temperature this matters less than the leakage and latch-up arguments, but it is not nothing.
What SOI costs you
Self-heating. Buried oxide is a good electrical insulator and a poor thermal one. Silicon dioxide conducts heat roughly a hundred times less well than silicon. A device dissipating power on an SOI island has a worse thermal path to the package than the same device in bulk, so its local junction temperature runs above the ambient the datasheet quotes. In a part that is already at 200 °C ambient, a self-heating rise of tens of degrees is not a rounding error — it has to be in the model, and it has to be in the layout strategy.
Floating body effects. If the body of an SOI transistor is not tied, charge accumulates in it and modulates the threshold voltage. The consequences have names: the kink effect in the output characteristic, history dependence where a device’s behaviour depends on what it was doing previously, and parasitic bipolar action. Body-tied device styles remove most of this at the cost of area and some layout freedom. For precision analog, body ties are usually not optional.
Cost and access. SOI wafers are more expensive than bulk, and fewer foundries offer high-temperature-qualified SOI processes with the model coverage and the device library a mixed-signal design needs. That narrows supplier choice, which matters over a product lifetime measured in a decade or more.
When bulk is still the right answer**
SOI is not automatic. Bulk CMOS remains reasonable when:
The upper limit is moderate. Below roughly 150 °C, careful bulk design with guard rings, generous well contacts and attention to the bias architecture can meet a lot of requirements. The leakage penalty is real but manageable.
The design is mostly digital. Digital circuits tolerate leakage far better than precision analog does; the cost is standby current rather than lost accuracy.
Volume dominates the decision. For high-volume parts the wafer cost difference is a real commercial input, and a bulk design that meets specification is cheaper than an SOI design that exceeds it.
A specific process has what you need. Process choice is not only about the substrate. Available passives, isolation options, thick-oxide devices for the supply rail, model quality at temperature, and the foundry’s own qualification data can outweigh the substrate question.
How the decision actually gets made
In practice the substrate question is not decided in isolation. It falls out of four inputs.
The temperature and lifetime pair. Not the maximum temperature alone, but the temperature profile and the required service life, because both wear-out and leakage are integrated over time.
How much of the design is precision analog. References, converters and high-impedance front ends set the leakage budget. Digital blocks do not.
Whether the environment can inject current. Long cable runs, inductive loads and hot-plug events all push current into pins. In bulk, that is a latch-up conversation. In SOI, it is not.
What is actually available and qualified. A process that is ideal on paper and unavailable at the volume and lifetime you need is not a choice.
Being fabless makes this a genuine decision rather than a constraint. When the process is not fixed in advance, the substrate can be chosen for the application rather than the application shaped around a substrate.
If you are at the stage where the process has to be chosen, the useful conversation is about the envelope, the accuracy that has to hold across it, and the service life. Those three answers narrow the options quickly.